1. Field of the Invention
The present invention relates to a voltage generating circuit, and particularly to a voltage generating circuit for clamping or regulating the output voltage of a boosting power source circuit or negatively boosting power source circuit.
2. Description of the Related Art
Flash memories serving as non-volatile semiconductor storage devices have been recently required to perform data reading and data rewriting by using a single power source source, and thus a voltage generating circuit for generating a boosted voltage or negatively boosted voltage is needed on-chip. Furthermore, the flash memories are required to be estimated, and thus a mechanism for applying the voltage corresponding to the boosted voltage or negatively boosted voltage from the external.
A conventional voltage generating circuit will be described hereunder with reference to the drawings.
FIG. 31 is a block diagram showing the construction of the conventional voltage generating circuit. In the Fig., 900 represents a boosting circuit for boosting a power source voltage Vdd and generating a boosted voltage, 901 represents the output of the boosting circuit 900, 902 represents a reference voltage generating circuit for generating a reference voltage Vref from the power source voltage Vdd, 903 represents a limiter circuit for setting the output voltage of the boosting circuit 900 to a desired voltage, 904 represents a resistor R1, 905 represents a resistor R2, 906 represents a voltage dividing circuit comprising a resistor 904 and a resistor 905, 907 represents the output of the voltage dividing circuit 906, 908 represents a differential amplifier circuit that is supplied with the boosted voltage from the output 901 and compares the voltage of the output 907 and the reference voltage Vref to carry out differential amplification, 909 represents the output of the differential amplifier circuit 908, 910 represents a P-type MOS transistor for extracting the voltage of the output 901 to the power source Vdd in accordance with the voltage of the output 909, 911 represents a regulator circuit for level-shifting the voltage of the output 901 to a desired voltage, 912 represents a resistor R3, 913 represents a resistor R4, 914 represents a voltage dividing circuit comprising a resistor 912 and a resistor 913, 915 represents the output of the voltage dividing circuit 914, 916 represents a differential amplifier circuit that is supplied with the boosted voltage from the output 901 and compares the voltage of the output 915 and the reference voltage Vref to carry out differential amplification, 917 represents the output of the differential amplifier circuit 916, 918 represents a P-type MOS transistor for setting the output Vp1 of the regulator circuit 911 to a desired voltage in accordance with the voltage of the output 917, and 919 represents a pad for applying a voltage from the external.
The circuit operation of the voltage generating circuit thus constructed will be described with reference to FIGS. 31 and 32.
A booted voltage VPh generated from the power source voltage is supplied to the limiter circuit 903 by the boosting circuit 900. A voltage of (γ×Vph) is applied to the output of the voltage dividing circuit 906 on the basis of the resistance ratio γ (=R2/(R1+R2) of the resistor 904 and the resistor 905. The reference voltage Vref generated from the power source voltage is compared with (γ×Vph) in the differential amplifier circuit 908 to control the gate voltage of the P-type MOS transistor 910 and adjust the drain current to be extracted from the output 901 to the power source Vdd, thereby keeping the boosted voltage Vph constant. With the foregoing operation, the boosted voltage Vph becomes a voltage satisfying Vph=Vref(1/γ) because Vref=(γ×Vph). That is, the boosted voltage Vph is not dependent on the power source voltage and keeps a constant voltage value for Vph>Vref×(1/γ).
The boosted voltage Vph is supplied to the regulator circuit 911. When a voltage Vpl achieved by level-shifting Vph is applied to the voltage dividing circuit 914, a voltage of (ξ×Vpl) is applied to the output of the voltage dividing circuit 914 on the basis of the resistance ratio ξ (=R4/(R3+R4) of the resistor 912 and the resistor 913. The reference voltage Vref generated from the power source voltage is compared with (ξ×Vpl) in the differential amplifier circuit 916 to control the gate voltage of the P-type MOS transistor 918 and adjust the drain current to be supplied from the output 901 to the output of the regulator circuit 911, thereby keeping Vpl constant. With the above operation, the output voltage Vpl of the regulator circuit 911 becomes a voltage satisfying Vpl=Vref×(1/ξ) because Vref=(ξ×Vpl), and it is not dependent on the power source voltage and keeps a constant voltage value for Vpl>Vref×(1/ξ).
When the characteristic of a flash memory cell is estimated, the voltage Vppex corresponding to the boosted voltage is applied from the external through the pad 919.
The above conventional technique is directed to the description on the voltage generating circuit for boosting the power source voltage and generating a boosted voltage higher than the power source voltage. The foregoing is applied to a conventional voltage generating circuit for generating a lower voltage than the ground voltage. That is, the construction that the boosting circuit 900 is replaced by a negatively boosting circuit, the ground connected to the voltage dividing circuits 906 and 914 is replaced by a reference voltage, the reference voltage input to the differential amplifier circuits 908 and 916 is replaced by the ground and the P-type MOS transistors 910 and 918 are replaced by N-type MOS transistors is a voltage generating circuit for generating, from a negatively boosted voltage, a constant negative voltage which is not dependent on the power source voltage. The negative voltage generating circuit as described above is also equipped with abnegate pad for applying a negative voltage from the external.
As one of the voltage generating circuits of the above conventional technique is known a voltage generating circuit having a mechanism in which the differential amplifier circuit 918 is driven with a power source voltage Vdd to reduce the power consumption of the boosted voltage to generate a constant voltage (Referring to JP-A-2001-52489)
However, the limiter circuit 903 and the regulator circuit 911 of the conventional voltage generating circuit can output only a fixed voltage with respect to the power source voltage as shown in FIG. 32. This is also applied to the negative voltage generating circuit.
The following problems occur when the conventional voltage generating circuit as described above is applied to a memory circuit (for example, a flash memory cell shown in FIG. 33).
First, the construction of the flash memory cell is shown in FIG. 33. In FIG. 33, 920 represents a voltage generating circuit, 921 represents a row decoder, 922 represents a column driver, 923 represents a column decoder, 924 represents a power switch circuit, 925 represents a flash memory cell array, 926 represents a P-type flash memory cell, 927 represents a P-type selection transistor and 928 represents an N-type MOS transistor.
In the flash memory cell as described above, a flash memory cell as a reading target is determined by the row decoder and the column decoder in the data reading operation. At this time, the power source voltage Vdd is applied to Vwell, Vsl, Vcg, however, the ground voltage is applied to Vsg of the P-type selection transistor. Therefore, there is a problem that the cell current is varied due to variation of the power source voltage Vdd and the dependence degree of the reading speed on the power source voltage is increased.
Furthermore, at the data writing time, the power source voltage Vdd is applied to Vwell, and a negative boosted voltage which is constant irrespective of the power source voltage Vdd is applied to Vbl and Vsg while a positive boosted voltage which is constant irrespective of the power source voltage Vdd is applied to Vcg. Therefore, Vwell−Vbl and Vwell−Vcg that determine the data writing speed are varied due to variation of the power source voltage Vdd, and thus there is a problem that the data writing speed is greatly varied.
The variation of the device characteristic due to the voltage variation, that is, the variation of the circuit characteristic can be suppressed by keeping the drain current of the P-type MOS transistor and the N-type MOS transistor constant irrespective of the power source voltage Vdd. However, there is a problem that a boosted voltage or negatively boosted voltage cannot be supplied in conformity with the characteristic of a supply load.
When the memory cell is estimated, it is required to apply the voltage corresponding to the boosted voltage to the pad or apply the negative voltage corresponding to the negatively boosted voltage to the negative pad, and surge breaking may occur under the high voltage application.